1. Field of the Invention
The invention relates generally to stackable tier structures comprising microelectronic circuitry. More particularly, the invention relates to stackable tier structures comprising one or more integrated circuit die and one or more area interconnect or “feedthrough structures”, which tiers may be stacked and interconnected to create compact, three-dimensional microelectronic modules.
2. Description of the Related Art
The ability to form very thin, stackable layers, each containing one or a plurality of homogeneous or heterogeneous integrated circuit chips is desirable and allows high density, high speed electronic systems to be assembled for use in military, space, security and other applications.
Examples of such layers and modules, referred to as “neo-layers” or “neo-stacks” are disclosed in U.S. Pat. No. 6,797,537, Method of Making Stackable Layers Containing Encapsulated Integrated Circuit Chips With One or More Overlying Interconnect Layers, U.S. Pat. No. 6,784,547, Stackable Layers Containing Encapsulated Integrated Circuit Chips With One or More Overlying Interconnect Layers, U.S. Pat. No. 6,117,704, Stackable Layer Containing Encapsulated Chips, U.S. Pat. No. 6,072,234, Stack of Equal Layer Neo-Chips Containing Encapsulated IC Chips of Different Sizes, and U.S. Pat. No. 5,953,588, Stackable Layers Containing Encapsulated IC Chips, all of which are incorporated fully herein by reference and all of which are assigned to Irvine Sensors Corp., the assignee herein.
The stacking and interconnection of very thin microelectronic layers allows high circuit speeds in part because of short lead lengths and related reduced parasitic impedance and electron time-of-flight. These desirable features combined with a very high number of circuit and layer interconnections allows relatively large I/O designs to be implemented in a small volume. What is needed is a structure that combines the above attributes but that can be fabricated using well-defined processes at relatively low cost.